Method and machine for examining wafers

ABSTRACT

Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention is a continuation in part of the patent application in title of “Method and Machine for Examining Wafers” with application Ser. No. 12/370,913 filed in Feb. 13, 2009, currently pending, all of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a method for examining wafers, and more particularly, to a method of weak point inspection for improving manufacture yield in semiconductor industry by using a charged particle beam tool.

BACKGROUND OF THE INVENTION

An integrated circuit (also referred to as IC, chip, or microchip) is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material. Additional materials are deposited and patterned to form interconnections between semiconductor devices.

ICs were made possible by experimental discoveries showing that semiconductor device could perform the functions of vacuum tubes and by mid-20^(th)-century technology advancements in semiconductor device fabrication. The integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using discrete electronic components. The integrated circuit's mass production capability, reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors.

In the early days of integrated circuits, only a few transistors could be placed on a chip, as the scale used was large because of the contemporary technology, and manufacturing yields were low by today's standards. As the degree of integration was small, the design was done easily. Over time, millions and today billions, of transistors could be placed on one chip, to make a good design become a task to be planned thoroughly.

ICs have consistently migrated to smaller feature sizes over the years, allowing more circuitry to be packed on each chip. In general, as the feature size shrinks, almost everything improves—the cost per unit and the switching power consumption go down, while the speed goes up. However, ICs with nanometer-scale devices still incur their original problems, principal among which is leakage current, although these problems will likely be solved or at least ameliorated by the introduction of high-k dielectrics.

Semiconductor ICs are fabricated in a layer process which includes these key processes: deposition, patterning, removal, and modification of electrical properties.

-   -   Deposition is any process that grows, coats, or otherwise         transfers a material onto the wafer. Available technologies         comprising physical vapor deposition (PVD), chemical vapor         deposition (CVD), electrochemical deposition (EPC), molecular         beam epitaxy (MBE) and more recently, atomic layer deposition         (ALD) among others.     -   Patterning covers the series of processes that shape or alter         the existing shape of the deposited materials and is generally         referred to as lithography. For example, in conventional         lithography, the wafer is coated with a chemical called a         photoresist. The photoresist is exposed by a stepper, a machine         that focuses, aligns, and moves the mask, exposing select         portions of the wafer to short wavelength electromagnetic         radiation. The unexposed regions are washed away by a developer         solution. After etching or other processing, the remaining         photoresist can be removed by plasma ashing.     -   Removal processes are any that remove material from the wafer         either in bulk or selectively and consist primarily of etch         processes, either wet etching or dry etching.         Chemical-mechanical planarization (CMP) is also a removal         process used between levels.     -   Modification of electrical properties has historically         comprising doping sources and drains of a transistor originally         by diffusion furnaces and later by ion implantation. These         doping processes are followed by furnace anneal or in advanced         devices, by rapid thermal anneal (RTA) which serve to activate         the implanted dopants. Modification of electrical properties now         also extends to reduction of dielectric constant in low-k         insulating materials via exposure to ultraviolet light in UV         processing (UVP).

Modern chips have up to eleven metal levels produced in over 300 sequenced processing steps.

In order to achieve the setting yield, the yield management of a fab needs to monitor, classify, eliminate or avoid defects from all kind of processes. A wafer map analysis has been developed for detecting and classifying patterns or process signatures based on low-resolution (e.g., 0.5 um/pixel) optical defect image distribution. As wafers exit a fabrication process, wafer map data is generated by an in-line defect detection workstation incorporating a microscopy or light-scattering system. The information in the wafer map consists of detected defect coordinates as well as process information such as step, layer, and product. The wafer map data may be combined across wafers to further view the evaluation of process signatures which may assist in diagnosing manufacturing problems.

As the feature size shrinks, ICs yield improvement by defect reduction becomes more and more important. A pre-analysis of signatures of a process or a structure with computer workstation starts with using graphical database system (GDS) to construct photomask for a die, then to utilize the computational lithography to numerically simulate, and to improve the performance (resolution and contrast) of cutting-edge photomasks. Next optical proximity correction (OPC) process is introduced in the modern semiconductor manufacturing. The OPC uses computational methods to counteract the effects of diffraction related blurring and under-exposure by modifying on mask geometries with means:

-   -   Adjusting line-widths depending on the density of surrounding         geometries (a trace surrounded by a large area will be         over-exposed compared with the same trace surrounded by a dense         pattern).     -   Adding “dog-bone” end caps to the end of lines to prevent line         shortening.     -   Correcting for electron beam proximity effects.         The computer-aid pre-analysis will illustrate a possible defect         distribution positions within the IC which is named “hot spots”         to the ICs yield management.

As a part of the wafer map process, an off-line defect review station examines these hot spots with a high resolution microscope, e.g., a defect inspection/review tool comprising scanning electron microscope (SEM), and classifies the defect according to individual morphology, color, texture, and relationship to process or layer.

The defect inspection/review tool proceeds wafer inspection/review job according to a process instruction called a “recipe”. A “recipe” is a set of operating instructions (a processing program) that educates a tool how the tool should perform the process. The recipe varies for each kind of machine, and even among different machine manufactures for the same kind of machine. For example, an etch system by Applied Materials of Santa Clara, Calif. may require a 10-minute reaction time with a certain flow of gases, while the reaction chamber is kept at a certain elevated temperature. At the end of the 10-minute reaction time, the flow of reactive gases is gradually reduced and replaced with inert gases as the temperature is lowered. Another etch system by Lam Research of Fremont, Calif. may require a 15-minute reaction time, with a different mixture of gases and a different temperature. Other kinds of semiconductor processing equipment require vastly different recipes. These recipes can become quite complex and vary as process engineers attempt to tweak the process for desired electrical and manufacturing-yield results. Different semiconductor products may require different recipes or combinations of steps. A DRAM process may require lighter ion implant doses than a process for logic chips and different oxide thicknesses require different reaction time in the furnace.

The recipe for a defect inspection/review tool contains instructions such as (a) product information that record the current inspection is after what semiconductor process; (b) inspection parameters that set the inspection tool, detecting area; and (c) detecting parameters that instruct the tool what to do in the detecting area. As an SEM-based defect inspection/review tool provides images at high resolution (e.g., 0.01 um/pixel), however, the throughput of a fully examined wafer (e.g., 24 hours/wafer) is away below the expectation (e.g., 1 wafer/hour).

The wafer map analysis illustrates defects distribution after processing, in which the defect clustering area on the wafer is called “weak points” of the wafer. In order to meet the throughput requirement, a recipe instructs the inspection/review tool to perform the inspection according to the weak points might be a solution.

The present invention provides a weak point inspection method performed by a charged particle beam inspection/review tool to meet the throughput requirement in semiconductor manufacturing.

SUMMARY OF THE INVENTION

A weak point inspection method is disclosed. The present invention utilize high resolution SEM with SORIL objective lens, smart review sampling filter, and universal defect identification unit to construct wafer map and perform weak point inspection of the wafer and/or the “lot” of wafers accordingly.

The weak point inspection method examine only the critical area of a wafer defined by a predetermined wafer map instead of the whole wafer to enhance inspection throughput.

The weak point inspection method updates the wafer map of a specific process or a specific device after each wafer has been examined through. Therefore the weak point algorism of the present invention has self-learning ability.

The weak point inspection method may construct the “lot” own wafer map if no previous hot spot information can be referred to.

A machine to perform weak point inspection of wafers is equipped with a high resolution SORIL objective lens. The machine also is equipped with a smart review sampling filter to confine inspection area defined by wafer map, the universal defect identification unit to identify and classify defects.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustration of a prior art imaging unit.

FIG. 2 is a schematic diagram illustration of a prior art defect finding algorism.

FIG. 3 is schematic diagram illustration of an inspection tool structure for examining wafers in accordance with an embodiment of present invention.

FIG. 4 is a schematic diagram illustration of a flowchart to perform weak point inspection in accordance with an embodiment of present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to specific embodiments of the invention. Examples of these embodiments are illustrated in accompanying drawings. While the invention will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to these embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a through understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process operations are not described in detail in order not to unnecessarily obscure the present invention.

Terminology definition:

-   -   in the present invention “examine a wafer” implies the wafer is         inspected by a charged particle beam system after the wafer         experienced a semiconductor fabrication process in a process         tool.     -   In the present invention “a “lot” of wafer” implies a group of         semiconductor wafers that will experience a semiconductor         fabrication process with a same process tool as a batch or one         wafer at a time. The number of wafers within “a lot” may be one         or several wafers in a wafer cassette, or more than one         cassette. Typically, one cassette may contain at most 25 200-mm         wafers or 13 300-mm wafers.     -   In the present invention “hot spot” of a wafer of a         semiconductor process implies a possible defect location within         a die or a device provided by a prediction of a numerical         simulation, a verified result of a previous inspection output of         other defect scanning tool (e.g., a klarf file), and a         historical wafer map result collected from previous wafers which         experienced all fabrication processes.     -   In the present invention “weak point” of a wafer implies a         defect clustering area which is illustrated through wafer map         analysis.     -   In the present invention a scanning electron microscope (SEM)         will be use as an example to express a charged particle beam         system.

Wafer inspection tools help semiconductor manufacturer increase and maintain ICs yield. The IC industry employs inspection tools to detect defects that occur during the fabrication process. The important characteristics of an inspection tool are defect detection sensitivity and wafer throughput. Sensitivity to detect a defect and wafer throughput are coupled such that greater sensitivity usually means lower throughput.

An scanning electron microscope (SEM) based inspection tool, for example, has an inspection probe spot diameter of 100 nm and a pixel rate of 12.5 million pixels per sec (Mpps), has a throughput of 0.05 300-mm wafers per hour (wph). A throughput at this level can not bear to do a full wafer inspection after a fabrication process. In order to perform valuable tool time to inspect critical position, a “hot spot” inspection and or a “weak point” inspection with a high resolution charged particle beam inspection tool is developed. FIG. 1 illustrates a SEM-based high resolution defect inspection/review tool with a swing objective retarding immersion lens (SORIL) developed by Chen et al. (U.S. Pat. No. 7,960,697), all of which is incorporated herein by reference. The beam tube 150 and the immersion magnetic field objective lens 182 provide high image resolution imaging unit for the present invention. The EDS detector 172 added to the modified SORIL 180 also provides an ability of identifying composition of defects.

U.S. patent application Ser. No. 13/303,953 in titled of “Smart Defect Review for Semiconductor Integrated Circuit” by Wang el al., filed in Nov. 23, 2011, all of which is incorporated herein by reference. As shown in FIG. 200, the present invention adopted the smart sampling review filter 240 algorism developed by Wang et al. to set up a defect inspection or defect review plan, which instruct the inspection/review tool to locate defects from a confined area instead of the whole wafer based on previous loaded information. The present invention also adopted the universal defect identification unit 250 algorism to identify defects through image comparison developed by Wang, et al.

Hot spot information of a specific semiconductor fabrication process with a specific processing tool may be come from numerical simulation, wafer map analysis, and output file from other defect scanning tool. A “recipe” is constructed for a SEM-base defect inspection/review tool to instruct tire tool perform defect inspection/review on those “hot spot” positions, to examine the possible defect positions with high resolution, to classify the real defect according to the defect shape, size, physical characteristics, and fabrication process. A wafer “weak point” map illustrates real defect distribution can be constructed after perform wafer map analysis according to the output of SEM-based defect review. Base on the result of the defect inspection/review tool, a fab manager can recommend corrective actions to the corresponding process or processing tool thereafter improve the yield of the fabrication process.

For a semiconductor fabrication process or processing tool that without previous experience to determine wafer “hot spot”, one embodiment of the present invention to set up the inspection/review tool's own “weak point” map according to the inspection/review result of previous wafers. FIG. 3 illustrates a block diagram describing the key composition of the tool that performs weak point inspection in the present invention. Block 301 the wafer load/unload assembly which consists with the loading unit 220 of FIG. 2: block 302 the recipe assembly which consists with the smart review sampling filter 240 of FIG. 2; block 303 the examining assembly which consists with the imaging unit 100 of FIG. 2; block 304 the defect-finding algorism which consists with the universal defect identification unit 250 of FIG. 2; block 305 the data management algorism which consists with the combination of two function block data classification 260 and data export 270 of FIG. 2. A wafer map regarding defect distribution is constructed at the block 305.

FIG. 4 illustrates a flowchart to perform the self “weak point” inspection according to one embodiment of the present invention. A “lot” of wafers is sent to the defect inspection/review tool 100 (will be refer as tool 100 here since) and a wafer is loaded. The recipe will check if a wafer map already exists in database regarding the loaded wafer, if the answer is no, the wafer is undergoing a full wafer inspection, a full wafer inspection plan is setup accordingly as the step 430 and 434 illustrated in FIG. 4. If the answer is yes, the wafer map is loaded from database and a “weak point” inspection plan is setup to cover the defect located area according to the wafer map indicates (step 420, and step 424). The step 422 is for checking if the information of wafer map can represent the incoming wafer or not. If the answer is no, the recipe will back to step 430 and perform a full inspection for the loaded wafer, if the answer is yes then the recipe will perform step 424 to set up an inspection plan only to cover the critical area that indicates by the wafer map.

The tool 100 will identify defects in step 440 using algorithm of the universal defect locating unit 250. There are several methods can be chosen for defect identification. Three points comparison method, the method identify defects by comparing images acquired from three different positions and mark error (defect) on the one deviate from the other two images. Die to golden die, the method identify defects by comparing images acquired from one die of the loaded wafer and a golden die to distinguish if a defect exists, where the golden die is refer to a perfect die without any defects. Die to design database or die to database, the method identify defects by comparing images acquired from a layout for a die or device of the loaded wafer and the original layout for a else or device on the design database.

The following step 450 is wafer mapping, this step records defects and its die/wafer location to database. The defect classification information such as defect type, size of the defect, composition of the defect if applied, process history of the wafer, coordinates on the wafer, location of the die (local coordinates), and etc., are recorded. After wafer mapping, the tool 100 compares found defects position on the current wafer map and the previous wafer map. If the defects' position consistency is over 99% then set flag=1. Flag=1 indicates that the wafer map can pretty much represent the defect clustering area of a wafer in this “lot” and a weak point inspection plan setup according to this wafer map may cover most of the defect clustering area. If the defects' position consistency is less than 90% then set flag=0. Flag=0 indicates next wafer will perform full wafer inspection again to accumulate defect distribution information. The tool 100 utilizes the smart review sampling algorithm 240 to construct the weak point inspection plan to save inspection time when Flag is set to 1.

Step 460 releases the wafer after inspection and in step 470 the recipe will request next wafer within the “lot” if there is any, the recipe will end the batch job in step 480 if no more wafer need to be inspected within the “lot”.

It is because the information of the new discovered defect within the specified area will be updated to the wafer map database, therefore the weak point algorism of the present invention has self-learning ability. Since the inspecting area of the next wafer loaded is varied according to the previous inspection results, in another words, the recipe of the inspection is varied in each inspection process.

The first advantage of the present invention is increasing throughput by focusing inspection area on critical or weak point area on the wafer. The second advantage of the present invention is that knowledge learned will accumulate automatically onto the database.

Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that other modifications and variation can be made without departing the spirit and scope of the invention as hereafter claimed. 

What is claimed is:
 1. A method of inspecting a wafer, comprising: determining whether a map stored in a database represents the wafer; determining a first inspecting plan according to a critical area to define an inspection area on the wafer when a first condition is satisfied that is based on similarity of the critical area to the map, otherwise determining a second inspecting plan, wherein the first inspecting plan covers only a defect inspection area indicated by the map; examining the wafer with a high resolution imaging tool using the first inspecting plan or the second inspecting plan; and identifying defects in the inspection area according to at least one image taken by said high resolution imaging tool.
 2. The method of claim 1, wherein the first inspecting plan is constructed by a smart review sampling filter.
 3. The method of claim 1, wherein the high resolution imaging tool contains a swing objective retarding immersion lens (SORIL) objective lens.
 4. The method of claim 1, wherein the defect is identified by a universal defect identification unit.
 5. The method of claim 1, wherein the map comprises at least one of the following: a possible defect location within a die or a device provided by a prediction of a numerical simulation; a verified result of a previous inspection output of other defect scanning tool; and a historical wafer map result collected from a previous wafer that experienced all fabrication processes.
 6. The method of claim 1, wherein the critical area comprises a possible defect location.
 7. The method of claim 6, wherein the possible defect location comprises a forerunner to defects.
 8. The method of claim 1, further comprising determining the critical area based on a prediction of a numerical simulation.
 9. The method of claim 1, further comprising determining the critical area based on a result of image processing.
 10. The method of claim 1, further comprising determining the critical area based on analysis of signatures of the wafer.
 11. The method of claim 10, wherein the analysis uses a graphic database system (GDS) file.
 12. The method of claim 1, wherein the first inspecting plan is determined based on at least one of the following: product information identifying a feature based on a semiconductor fabrication process; and detecting parameters that instruct the high resolution imaging tool what to do in the inspection area.
 13. The method of claim 1, wherein the first inspecting plan comprises instructions configured to cause the high resolution imaging tool to examine the wafer only in the critical area instead of the whole wafer.
 14. The method of claim 1, further comprising determining a first similarity between a wafer map representing the wafer and another wafer map stored in the database; in response to the first similarity exceeding a threshold, setting a wafer map flag value to a first value, otherwise setting the wafer map flag value to a second value; and constructing the first inspecting plan when the wafer map flag is the first value, otherwise constructing the second inspecting plan according to full wafer inspection.
 15. An apparatus comprising: a load/unload assembly configured to receive a lot including a wafer; a memory storing a set of instructions; and a processor configured to execute the set of instructions to cause the apparatus to: determine whether a map stored in a database represents the wafer; construct a first inspecting plan for inspecting the wafer according to a critical area to define an inspection area on the wafer when a first condition is satisfied that is based on similarity of the critical area to the map, otherwise determining a second inspecting plan, wherein the first inspecting plan covers only a defect inspection area indicated by the map; acquire at least one image of the wafer with a high resolution imaging tool using the first inspecting plan or the second inspecting plan; and identify defects in said inspection area according to the at least one image.
 16. The apparatus of claim 15, wherein the first inspecting plan is constructed by a smart review sampling filter.
 17. The apparatus of claim 15, wherein said high resolution imaging tool contains a swing objective retarding immersion lens (SORIL) objective lens.
 18. The apparatus of claim 15, wherein the defects are identified by a universal defect identification unit.
 19. The apparatus of claim 15, wherein the map comprises at least one of the following: a possible defect location within a die or a device provided by a prediction of a numerical simulation; a verified result of a previous inspection output of other defect scanning tool; and a historical wafer map result collected from a previous wafer that experienced all fabrication processes.
 20. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of an apparatus to cause the apparatus to perform a method for inspecting a wafer, the method comprising: determining whether a map stored in a database represents the wafer; determining a first inspecting plan according to a critical area to define an inspection area on the wafer when a first condition is satisfied that is based on similarity of the critical area to the map, otherwise determining a second inspecting plan, wherein the first inspecting plan covers only a defect inspection area indicated by the map; examining the wafer with a high resolution imaging tool using the first inspecting plan or the second inspecting plan; and identifying defects in the inspection area according to at least one image taken by said high resolution imaging tool. 